Viewing a single comment thread. View all comments

kiwifuel t1_j08eix1 wrote

Reply to comment by swisstraeng in Japan to Manufacture 2nm Chips With a Little Help From IBM by Avieshek

I don’t think that’s true. Nm (logic gage size) has to do with transistor density. And it is one of several important factors in performance.

I think the average density coming out of a foundry is somewhere between 7 and 14. A foundry i visited in the Texas is pushing 12 nm. Intel and AMD do 7 and 5nm respectively.

2nm is nearing the physical limit. And will serve as a bottle neck in future design. It’s pretty neat. It’s only a few atoms wide.

−3

g0ndsman t1_j08u6b4 wrote

I don't think the feature size of the technology is 2 nm. The performance might being line with a theoretical scaled 2 nm technology in at least some aspects, but transistors will be much bigger than that. All technologies stopped using actual transistor size (more precisely channel length) years ago as we moved away from planar transistors.

13

Murgos- t1_j0905kj wrote

Lambda used to mean the smallest size feature that could be reliably realized in the design. At the same time you still needed margin to carry current and to resolve any imperfections.

So the smallest thing you could make might actually had a minimum requirement of 2Lambda.

I don’t do ASIC gate layout any more but I expect that when they say 7nm now or 5 or whatever they really mean that they can resolve a 7nm feature but you still need 2 or 4 lambda to actually make it work.

2

swisstraeng t1_j09bh24 wrote

That's the thing, it is not a few atoms wide. Ask google, you'll learn something. You cannot make a transistor gate of only 5 or 10 atoms, due to quantum tunneling, but I mean, without the fancy quantum name, it just means that, there are probabilities electrons still get the energy to make the jump when we don't want them to. The gate's size is not two nanometers. It's around 40nm. Or bigger.

0