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swisstraeng t1_j07mua3 wrote

(friendly reminder that 2nm is a marketing name and has nothing to do with actual values compared to back when it used to, it's now just a name for a fabrication process)


Gavri3l t1_j07oc9n wrote

Thanks for this. I was really wondering how they managed to get past the quantum tunneling problem.


swisstraeng t1_j08a2s9 wrote

Well, they didn't. In reality the 2nm process has an expected gate size of around 45nm.

That doesn't mean they aren't finding cool ways to make the chips even more compact. Lots of less known terms like GAAFET. (some kind of vertical 3D transitors)

But the main issue with all of this, is that the prices to manufacture a single chip is higher and higher. Since now it's not a matter of size, but also of fabrication complexity and time.

If I were to guess, we'll get slowly stuck in 2025-2030 era regarding our current technology. I think this will be when we'll need to use alternatives, more power efficient ARM architecture, which is what Apple is already using for its M1 and M2 chips.


orincoro t1_j08c6qx wrote

Yeah, I thought I read this, that the obvious next step is to just build the wafers in a 3D architecture, but it’s super complicated to fabricate.


IlIIlllIIlllllI t1_j08pupi wrote

heat is a bigger problem


Hodr t1_j0bvehy wrote

Heat is more of a materials issue. Once they hit the wall they can move to GaAs or other semiconductors.

The only reason we still use silicon is the existing infrastructure and the relative abundance of the element.


swisstraeng t1_j09a5ge wrote

Yeah, and the main issue is that, when you add layers on top of layers, you are less and less flat. And at some point you're a whole layer wrong, so you have to do long and expensive processes to try to flatten the thing again.

Cooling is partially an issue, but that's also because CPU/GPU manufacturers push their chips to their limits in an attempt to make them appear better. And end up selling stuff like RTX4090 that is clocked way too high and end up eating 600W, when it could have 90% of the performances for 300W. But hey. They're not the ones paying the power bill.


orincoro t1_j0c7tzb wrote

I wonder how much electricity globally is consumed by needlessly overclocked GPUs.


swisstraeng t1_j0ei32s wrote

Surprisingly not much. If we only look at industry grade hardware. Consumers? Yeah, a lot is wasted.

All server and industrial stuff is actually not too bad. For example, the chip used in the RTX 4090 is also used in a Quadro card.

It is the AD102 chip. Used in the RTX 6000 Ada gpu, which has only 300W TDP compared to the RTX 4090 that has 450W and is pushed to 600W sometimes. Or worse, 800W in the RTX 4090ti.

We're talking about the same chip and a 300W versus 800W difference.

Anyone using a rtx 4090ti is wasting 500W into a bit of extra computing power.

But hey, kwh costs about 0.25euros in the EU depending where you live. This means, you pay 1 euro every 8h of use for a rtx4090ti that could be saved by downclocking the card.


SneakyCrouton t1_j09z32d wrote

See that's just a marketing name for it, it's actually just a 2D transistor but they draw a little D on there for legality purposes.


Jaohni t1_j09jjfj wrote

PSA: ISA =/= implementation.

While it was common to suggest in the late 90s and early 2000s that there was a strong distinction between CISC and RISC styles of architecture, owing to CISC having a wide variety of purpose built instructions that aided in accomplishing specific tasks quickly, while RISC would have fewer transistors sitting around doing nothing (idle transistors do still consume some power, btw) as a consequence of bloated instruction sets, in reality, modern ISAs have a mix of CISC and RISC philosophies built in, and more important than a core being ARM or x86, is the way that core is implemented.

In reality, if you look at a variety of implementations of ARM cores, there actually isn't as big an efficiency improvement gen over gen as you would expect, as seen in the Snapdragon 865, 870, 888, and 8 gen 1 all performing relatively closely in longer tasks (though they do benchmark quite differently in benchmarks that test a series of tasks in very short bursts), and actually not being that out of line with certain x86 chips, such as something like a 5800X3D (were one to extrapolate its performance when compared to a 5800X power limited to similar wattage to the SD SoCs), or say, a Ryzen 6800U processor power limited to 5W.


That's not to say that there isn't ARM IP out there that can be beneficial to improving performance at lower power draw, but I'd just like to highlight that a lot of the improvements you see in Apple Silicon aren't necessarily down to it being ARM, but due to it being highly custom, and due to Apple having varying degrees of control over A) the hardware, B) the drivers / OS / software stack, and C) the actual apps themselves. If you're able to optomize your CPU architecture for specific APIs, programming languages, use cases, and operating systems, there's a lot of unique levers you can pull as a whole ecosystem, as opposed to say, just a platform agnostic CPU vendor.

Another thing to note is that while Apple saw a very respectable increase when jumping from Intel to their in house M1 chips, it's not entirely a fair comparison between x86 and ARM as instruction sets, as the Intel implementation was implemented on a fairly inferior node (14 nanometer IIRC), while the M1 series was implemented on a 5nm family node, or possibly more advanced. When taking this into account, and comparing the Intel versus M1 macs, you may want to remove anywhere between 80 to 120% of the performance per watt improvements to get a rough idea of the expected impact of the node, with what's left being a combination of the various ecosystem controls Apple has available.

When compared to carefully undervolted Raptor Lake chips, or equally carefully managed Zen 4 processors, the Apple SoCs, while respectable in what they do (and being respectable as a result of many things not owing to their ARM ISA), they aren't alien tech or anything; they're simply a well designed chip.


frozo124 t1_j09mnnx wrote

It’s true. I work for ASML and things keep getting smaller


Ultra-Metal t1_j093vt3 wrote

Well, you have to do that for the gate until they come up with something better. Quantum tunneling is very much a thing at this size.


Mango1666 t1_j08v67v wrote

idk if gaafet will come to consumers in the capacity finfet and mosfet have reached, gaa is a very supply limited substance in comparison!


jjayzx t1_j08zqx2 wrote

What do mean substance? GAAFET(Gate All Around FET) is a design, not a material.


swisstraeng t1_j09bv7d wrote

True that it's not a material, BUT there is a valid point that, such 3D ways of doing transistors are expensive to manufacture.

And we, consumers, don't like expensive things. We want performance/price most of the time.

Not a lot of us would be ready for a 4000$ CPU if it meant 30% better perfs over a 900$ CPU.


jjayzx t1_j09ddkj wrote

Different designs is how things have been moving forward and how they've been targeting the performance/price ratio. If the device does not require much processing power there are other processors still made on older nodes for a lower price point. The majority of pricing is in the machines, wafers and yields.


dreamwavedev t1_j0abb8c wrote

I think you might mean GaN which is a different semiconductor material they're using in some power supplies.

GAA stands for gate-all-around and describes the geometry of the transistors (the gate surrounds the channel on all sides, FinFET was just surrounding it on 3 side) not what they're made of


Phyltre t1_j082kzr wrote

I love when marketing does stuff like "etymology doesn't real, sure the acronym/initialism used to have a meaning but we've retroactively altered it--now KFC doesn't stand for anything." Feels inherently dishonest. You want it to not stand for something, change the name from the characters that do have a history of standing for something. Connotations aren't a matter of explicit unilateral control.


tr3v1n t1_j08m90j wrote

> Feels inherently dishonest.

It is dishonest, but it also stems from the fact that people got so focused on the numbers that they kept shrinking them because otherwise people wouldn't think there are improvements. If I remember correctly, the number itself was never actually super accurate as the different processes would measure things differently.


hellhoundtheone t1_j07oers wrote

Are you saying they can produce 2 NM Chips but that doesn’t mean those chips are great ?


MuhCrea t1_j07q1st wrote

He's saying a 2nm chip doesn't actually measure as 2nm


rgpmtori t1_j08a9pa wrote

Normally nm means nano meter, it used to be very important to have smaller and smaller sizes for a variety of reasons which improved speed of computers. Ability to produce chips at a smaller nm meant drastic performance improvements like 15 years ago


Sirisian t1_j07zhey wrote

Just to be clear the nodes do refer to upgrades generally. So both speed and power usage gains. Just as things get closer to literally buildings with atoms the terminology falls apart. The small structures are 3D arrangements, so one measurement doesn't capture things anyway. Back when things were larger (like a decade ago) it made a lot more sense.


BoltTusk t1_j08eeby wrote

What’s “Intel 18A” then? Not 18 Angstroms?


swisstraeng t1_j09ahok wrote


1 Angstrom is 0.1nm, and it's first of all completely dumb to use non-standard units, when they could have said 100pm instead.

Intel just ran out of numbers to write, so they used the next available scale: angstrom.

But again, that's just a marketing number.

Intel calls it 18A. TSCM calls it N2, samsung calls it 2GAP. But all those fancy names are just factory processes. Ways to make silicon chips. Those processes are currently done in laboratories and being researched, and are expected to be used around 2025 for production.


WHAT_DID_YOU_DO t1_j09o1el wrote

TBF to angstrom that is the length of atomic bonds so it’s a lot easier to say a carbon atom is a little over an angstrom than 130 pm

Agreed on most other non-standard measurements though


Arodg25 t1_j0969zp wrote

any idea why they choose to make this confusing?


swisstraeng t1_j09967i wrote

Simply put: Engineers said they can't make it smaller, it didn't stop marketing people that thought it was a good idea.

It's as dumb as 2666Mhz ram, that in reality is clocked at 1333MHz, and 2666's proper unit of measurement is MT/s.

Why? Because DDRx ram stands for double data rate. Marketing wanted to use larger numbers because it sounded like it'd sell more ram.

They ended up confusing everyone. Again.


Optimistic__Elephant t1_j09rezs wrote

Also how you end up with nonsense like this.


Aetherdestroyer t1_j0axlmf wrote

What is the problem with that?


eldelshell t1_j0be2j0 wrote

Once upon a time, shaves only had one blade and then, the race to add as many blades as possible started... Is a 10 blade shave better? No, but it's all marketing (my shave has 10 blades! I'm alpha af you single blade pleb)


Demibolt t1_j0ebxcd wrote

There actually are a lot of interesting reasons for the addition of additional, smaller blades instead of just 1 larger and very sharp blade.

But despite the marketing bs, basically more blades makes it easier for someone to get a close shave while reducing the chance of irritation - while also decreasing product durability. which are all positives to them.


InternetUnexplorer t1_j0bdx4g wrote

I feel like it kind of makes sense for DDR though? Even if it's not technically correct I feel like the reasoning is pretty straightforward. I don't mind the process names either though, so maybe that's it's just because I'm used to it…


Yancy_Farnesworth t1_j09xl5d wrote

> it's now just a name for a fabrication process

Yes and no. The process name is supposed to describe an improvement in transistor density now. As in for the same company, the next node is some % improvement over the previous one. They did this because below 7nm the nm measurement became even more meaningless for indicating transistor size/density.

> has nothing to do with actual values compared to back when it used to

Even when the measurement applied to the smallest "feature size", it still didn't describe the size of the actual transistors or transistor density. For example, Intel 10nm was more transistor dense then TSMC's 7nm process. Intel's 7nm process was targeting a higher density than TSMC's 5nm process. Intel fell behind TSMC because they tried to do it on DUV machines rather than EUV, which set them back years as TSMC wound up getting access to EUV equipment first. Hell, even with 7nm, TSMC's was better than Samsung's equivalent process.


kiwifuel t1_j08eix1 wrote

I don’t think that’s true. Nm (logic gage size) has to do with transistor density. And it is one of several important factors in performance.

I think the average density coming out of a foundry is somewhere between 7 and 14. A foundry i visited in the Texas is pushing 12 nm. Intel and AMD do 7 and 5nm respectively.

2nm is nearing the physical limit. And will serve as a bottle neck in future design. It’s pretty neat. It’s only a few atoms wide.


g0ndsman t1_j08u6b4 wrote

I don't think the feature size of the technology is 2 nm. The performance might being line with a theoretical scaled 2 nm technology in at least some aspects, but transistors will be much bigger than that. All technologies stopped using actual transistor size (more precisely channel length) years ago as we moved away from planar transistors.


Murgos- t1_j0905kj wrote

Lambda used to mean the smallest size feature that could be reliably realized in the design. At the same time you still needed margin to carry current and to resolve any imperfections.

So the smallest thing you could make might actually had a minimum requirement of 2Lambda.

I don’t do ASIC gate layout any more but I expect that when they say 7nm now or 5 or whatever they really mean that they can resolve a 7nm feature but you still need 2 or 4 lambda to actually make it work.


swisstraeng t1_j09bh24 wrote

That's the thing, it is not a few atoms wide. Ask google, you'll learn something. You cannot make a transistor gate of only 5 or 10 atoms, due to quantum tunneling, but I mean, without the fancy quantum name, it just means that, there are probabilities electrons still get the energy to make the jump when we don't want them to. The gate's size is not two nanometers. It's around 40nm. Or bigger.


BlueCheeseNutsack t1_j086zx2 wrote

I fucking hate that they use a literal size measurement as a marketing term, when it’s not that size.


Ralphinader t1_j07lilh wrote

"I get by with a little help from ibm"


JVM205 t1_j07psp4 wrote

“Hmmmm I can try, with a little help from IBM”


its8up t1_j07qadt wrote

"Do you neeeeeed techno-logy? I just need porn on my phone."


galgor_ t1_j081ecm wrote

Could it beeeee something more useful?? No I just need porn on my phone.


woahdude12321 t1_j08qbjh wrote

What do you do when a bugs in the way?? Can real tech support be reached from home


majesthar t1_j0bmq6m wrote

What do you mean with “the software doesn’t work?” It runs smoothly on my pc.


Leanardoe t1_j07iv7e wrote

reducing taiwan reliance? neat


Avieshek OP t1_j07j4tx wrote

With Japanese precision? Neat.


Eedat t1_j0856s9 wrote

Isn't the US in the process of building a giant manufacturing plant as well?


navigationallyaided t1_j086uz6 wrote

Intel is building a new fab near Columbus, OH. TSMC is building a new facility in Arizona - there is already an Intel fab in Chandler and I think Microchip has one in Tempe or Nogales. Samsung Austin fabs non-NAND/DRAM silicon.

The actual chip “packaging” - mounting it onto a substrate or encasing it in plastic and ceramic after attaching lead wires and pins/solder pads will still happen overseas - Intel does this in Costa Rica/Philippines, Samsung ships Austin silicon back to Korea or China, and China/Korea/Vietnam/Mexico/Philippines are were silicon is packaged.


BigMikeATL t1_j087rrt wrote

Yup. The Intel plant in Chandler is currently undergoing a $20B expansion. That’s in addition to the new TSMC plant.

Samsung is also building a huge semiconductor plant in Texas.


navigationallyaided t1_j08hvik wrote

Intel also has a fab in Hillsboro - but I haven’t heard plans for it.

The eventual goal with the new C-suite at Intel - they want to be a contract supplier. Many of the current IC companies who make important components or even whole systems like Qualcomm, Marvell, Nvidia, AMD and Apple don’t have their own fabs - TSMC and Samsung are doing that. I can see Apple and Intel becoming frenemies, much like the Apple-Samsung relationship. Companies that do work with the military or critical infrastructure might be compelled to have chips fabbed in the US as a matter of national security.


Unaninu t1_j0bpaur wrote

The one in Hillsboro is literally their main fab, where all the R&D and magic happens and where all the other fab will "copy exactly".


SargeInCharge t1_j0a1gay wrote

Don't forget Micron's new $15 billion plant in Boise


navigationallyaided t1_j0aczhs wrote

And that coincided with the tail end of IMFT - the Intel-Micron NAND joint venture. Intel saw Optane as the new hotness, high-bandwidth X-point NAND that was supposed to be paired with a mechanical SSD; the Windows version of Apple’s Fusion Drive.

It was a flop, much like Intel’s gamble on Rambus RDRAM 20 years ago - and Samsung took the NAND world by storm with their 3D V-NAND.


Kongsley t1_j094vlv wrote

>Microchip has one in Tempe or Nogales.

Lol Microchip doesn't belong on the same list as Intel, TSMC, and Samsung.


navigationallyaided t1_j099kpb wrote

You’d be shocked - anything that requires RF, like car key fobs, gate/garage remotes and discrete power/timing/IO, chances are those components are coming from Microchip, Intersil, ST Micro, ADC and National Semiconductor. Part of the electronics shortage - plenty of the “big” chips like DRAM/NAND, CPUs/GPUs/SoCs but not enough of the supporting cast like RF/discrete power/IO/networking/timing/battery monitoring - those are all specialized ICs that don’t use the latest and greatest process tech but have an important supporting role.


Kongsley t1_j09d1jl wrote

Yes, thank you for understanding and providing a list of manufacturers that Microchip does belong on.


navigationallyaided t1_j087a65 wrote

IBM has been in Japan for a while - the ThinkPad was designed at their Japanese operations. Lenovo has since bought out those facilities. I think they have a silicon fab there and the PowerPC architecture they developed along with Motorola was used heavily by the Japanese automakers and in gaming consoles.


zenithtreader t1_j0871ff wrote

I mean in the article they said it is expected to be produced before the end of this decade. TSMC is already planning to mass produce 3nm next year in 2023, it is very likely they would have something akin to 2nm by 2025 or 2026, still years ahead.

The fact is Japan has not been competitive in cutting edge chip fab for more than a decade and this is not something you can simply catch up by throwing money at it.


kiwifuel t1_j08eoek wrote

Well, money buys all the things that drive progress. But time is another factor.


Yancy_Farnesworth t1_j09wcxt wrote

They're not starting from scratch. IBM demonstrated their 2nm process over a year and a half ago, they were the first to do so. They're at the stage where they're getting it from the lab to production.

IBM's not a newcomer to the fab business, they've just been mostly focused on producing their own chips for their own enterprise/datacenter equipment rather than mass market equipment. I'm betting that this partnership is IBM eyeing the fab-only business model; or looking to get themselves fabless like how AMD divested themselves of their fabs and spun off Global Foundries.


LummoxJR t1_j08t6r7 wrote

In the same part of the world regularly threatened by the same toltalitarian scumbags threatening Taiwan? Less neat.


Tripanes t1_j09cd0g wrote

> with a little help from IBM

Japan to fail to produce 2 nanometer chips


drtij_dzienz t1_j09d5kk wrote

Had to scroll to the bottom to find the correct comment


37Schmeckles t1_j09d13j wrote

Meh, whatever the technical ramifications, go Japan.

Im all for manufacturing advancements happening in stable, peaceful democracies that dont want to take over the world or gut the human rights of their citizens.


iain420 t1_j09rtmv wrote

Tbf Japan does have some form on the "attempting to take over things" front


DiddlesYourDad t1_j0al1he wrote

“We know a little thing or two because we’ve seen a little thing or two.” -Japan, probably


SubbansSlapShot t1_j07lhqc wrote

“Before the end of this decade”. We will wait and see, but sounds exciting. Of course, not having to rely solely on Taiwan for chips is also a plus


zombimuncha t1_j07sf3h wrote

So if the west relies less on Taiwan for chips, does that make it easier or harder for China to take over?


SudoPoke t1_j07y70s wrote

It makes it harder diplomatically. It is and always has been militarily impossible due to geographic advantages. Anyone who says Taiwan is at any risk has no idea.


-Aerobrake- t1_j07zcup wrote

The chances that China can actually fully take over Taiwan are zero, but the chances that they can make a very stupid and doomed attempt at it and get millions of people on both sides killed before their inevitable defeat are much higher than zero.


SudoPoke t1_j0809xu wrote

yea agreed, only way china gets Taiwan is through mutual destruction and a city of ashes at the end.


fettuccine- t1_j07uja3 wrote

both. easier cuz its so close to China but hard because the US has strong presence in the area. also they wouldn't want to risk actually fighting there and destroy the fabs.


Silversky615 t1_j081eu0 wrote

The distance is irrelevant since it is an island. Russia hasn’t been able to take Ukraine and that’s a country right along their borders.

Trying to stage a D-Day invasion where each landing craft has thousands of soldiers in the age of accurate anti ship missiles is a death sentence.


TheArmoredKitten t1_j0839e6 wrote

Yeah it's just not physically possible to get the equipment for a conventional ground invasion into Taiwan. They'd have to do some kind of absolutely balls to the wall combined arms assault that perfectly coordinates an airborne invasion behind the beach defenses with the amphibious invasion, but even that would still probably fail gloriously as all those unsupported paratroopers would just be ripped to shreds by inland defenses and never even reach the objective.


Silversky615 t1_j083yj3 wrote

While a military invasion is unlikely I wonder what the likely hood of a Chinese blockade of Taiwan would be. I assume they will keep doing what they are already doing which is try to gain influence in Taiwan politically, but they messed that plan up after what they did to Hong Kong.


JelloSquirrel t1_j091lqh wrote

China wouldn't invade unless Xi is a true idiot.

China would subvert an election or bribe the military to do a coup supported by their special forces.


Eedat t1_j0866f7 wrote

They wouldnt dare touch large powers like the US or EU. They went full paper tiger about the Nancy Pelosi visit and the US just didn't care and did it anyway.

Taiwanese opinion on mainland China plummeted after they saw how Hong Kong was treated. Short term influence would be hard to gain


Pierogi_Master t1_j0875da wrote

Dexter Filkins talked about this on NPR Fresh Air recently. From memory a bit ago but basically as an island lots of things are imported, including the means of energy production. The island could be without power within a week or so of a blockade at the cost of 0 Chinese lives.

Elsewhere in the interview its mentioned that in war games the US simulates in an escalation that the US loses. One official stated we (the US) simply don't have the industrial base to manage a sustained conflict against the Chinese.


Silversky615 t1_j089cr2 wrote

I feel like these simulations never account for the advantage that absolute technological supremacy has. Similar to how with Russia the West would run out of shells in a very short amount of time, but who needs shells when they can not even begin to counter America’s full Air Force.


Pierogi_Master t1_j08b9bk wrote

These are run by the upper echelon of the Pentagon and others in DoD who WOULD take those things and others you (myself, and the public) dont know about into account.


TheArmoredKitten t1_j085esz wrote

The US would never stand for an actual blockade. It's too important to our interests and the USN would be leveling guns before Chinese ships even left port. If China so much as sneezed in the direction of an American commerical ship, Xi Jinping would find himself at the bottom of a crater before the end of the month.


kiwifuel t1_j08ezgc wrote

Take over what?

If the west relies less on Taiwan and semiconductor production is diversified, supply chains becomes more robust.

I would argue yes, chips manufactured in Japan gives China less economic leverage, but it’s complicated.


Yancy_Farnesworth t1_j09ug3j wrote

Neither. China has 0 access to the equipment that fabs leading node chips. People don't seem to understand that there's the fab process and then there's the fab equipment. TSMC, Samsung, and Intel all buy the same fab equipment from the same manufacturers, they don't make their own. All of those companies are from the US, the EU, and Japan. And it's impossible for them to keep these machines working without the expertise and replacement parts from the equipment manufacturers.

If China ever goes to war with Taiwan, they lose access to the entire semiconductor supply chain. Not to mention they also lose access to silicon wafer producers who are almost entirely US and Japan based.


asianclassical t1_j0a5vah wrote

Part of the reason the US is forcing companies like TSMC to build a fab in the US is to safeguard against the possibility that China retakes Taiwan, either militarily or politically. What people don't realize is that China doesn't have to physically take TSMC to get the technology. All of China's top semiconductor engineers come from TSMC. (There's also one famous one that defected to Samsung.) That's how China has been able to catch up so fast. This year an American company found that China was already producing a type of 7nm chip, when the industry previously thought it would take them 10-15 years to produce below 10nm.

Taiwan's problem is they are a neo-colony. TSMC is majority foreign-owned. They net between 40-50 billion USD a year. But that money doesn't go to the Taiwanese people. Salaries in Taiwan are notoriously low. The quality of life is maintained by keeping prices artificially low on the island, not by raising incomes. (You can see this in the wide discrepancy between nominal GDP and PPP) So it is relatively easy for the mainland to headhunt top TSMC engineers by offering double or triple what they were making before. Biden, taking a lead from Trump, just passed a series of massively protectionist measures without anybody noticing that would and have raised eyebrows of free-market economists:

>In addition, the rules require a license for any “U.S. persons”—which include citizens, permanent residents, anyone who lives in the country, and U.S. companies—to work with Chinese companies contributing to advanced semiconductor production in China. All of these groups have been forced to halt work with Chinese semiconductor firms. This has proven immediately damaging, as leading SME firms have had to stop all servicing of equipment at Chinese fabs and many of these machines need maintenance every couple days in order to continue running. In addition, the dearth of experienced U.S. talent will inhibit Chinese industry, since semiconductor fabrication requires the kinds of intangible skills built up over decades of engineering work and can’t be captured in a blueprint or instruction manual. Prior to the new rules announcement, many U.S., Korean, and Taiwanese engineers had responded to this need by taking lucrative positions in the Chinese semiconductor industry—echoing the way Taiwan built up its own chip industry in past decades.


Zeduca t1_j0bp238 wrote

Manufacturing and invention of processes are not the same, and are different from designing the chip.


29erfool t1_j07yb4d wrote

Ooh I get by with a little help from IBM 🎶


yodog5 t1_j08tkjo wrote

I really hope, for Japan's sake, that they covered their bases on this one and don't get fucked over by US export laws like Toshiba and others.


corgi-king t1_j0arv8a wrote

Given Japanese companies failed to make many successful semiconductor products in the past 20 years, I don’t have high hopes for this project.

Japan was dominated in 80-00 in high tech. But production costs is a major problem for them, given Korea then China flood the market with cheap and not too bad products in the market. Japan only have one major display manufacturer left even they invented most of the tech. Same thing for memory chips. The only semiconductor product that Japan still dominates is image sensor by Sony but the sensor don’t need to use latest chip making technology.

Also many major Japanese companies are too slow to react to market and too afraid of investment lost, but it makes sense in a way-just look at Toshiba, so they rather put money in bank than invest in new tech or manufacturing. This is kinda sad.


mngdew t1_j08hblo wrote

The article used it wrong. 2nm is the size of the chip manufacturing process, not the size of the chipset itself.


Zeduca t1_j0bolzd wrote

Those in the industry know what a 2nm chip means. Others don’t have the need to know.


iNfANTcOMA t1_j099z17 wrote

Fun fact HAL laboratories was named HAL because they were one step ahead of IBM.


TdrdenCO11 t1_j09rj7a wrote

chinese chip manufacturers hate this one trick…


mpworth t1_j0bg36m wrote

My whole life I’ve wondered why they produce the chips on circular wafers like that. Are the chips around the perimeter useless?


Optimistic__Elephant t1_j09rlck wrote

Optimistic__Elephant lands on the moon with a little help from Neil Armstrong.


Randomhouse131313 t1_j09t16w wrote

Yall remember when IBM provided technology to the Third Reich that allowed Nazis to persecute and kill Holocaust victims more efficiently??? Well Pepperidge farms remembers


necromundus t1_j0a0xzy wrote

With a little help

From an old friend


Competitive-Cow-4177 t1_j0b5u49 wrote

2nm transistors will not work consistently without producing mutual Electromagnetic Interference between the transistors, which (are now) too close together.

In the 2nm silicone these transistors are too close to each other & atoms will begin to electronically magnetically interact, causing false results flowing out of the transistors; making readings invalid.

5nm is the optimal size for a conventional transistor, for example look at M1 from Apple.


rroberts3439 t1_j0c93s5 wrote

So what's going to be the next step below the nm? Are they going to say .5nm? An attometer?


skhds t1_j0aralr wrote

Help from IBM? Does that even help