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Aceticon t1_iqo53tt wrote

I would really like to know how exactly these could help make smaller transistors in digital chips given that the current processes etch much smaller transistors in the sillicon substrate that the 50nm wire placements precision they've achieved with this process.

In fact, from all I know about chip manufacturing the only "wires" which are placed mechanically (rather than formed by chemical deposition) are the ones linking the chip pads to the pins in the chip package.

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Altiloquent t1_iqo7ngs wrote

And no idea how they envision moving a billion nanowires per chip onto a stamp with essentially no errors. Seems like a useful tool for researching nanowire properties though

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