Interesting fact. The silicon memory die has bond pads running down the centre and it is fitted face down. The package substrate has a slot running through the centre. The silicon is electrically connected to the bottom of the substrate (the side with solder balls) by wires stitched through the slot. This is then covered in a strip of mould compound visible in the image. Super fast signals, super cheap construction.
pi_designer t1_j1pspw3 wrote
Reply to Samsung develops industry’s first 12nm-Class DDR5 DRAM by thebelsnickle1991
Interesting fact. The silicon memory die has bond pads running down the centre and it is fitted face down. The package substrate has a slot running through the centre. The silicon is electrically connected to the bottom of the substrate (the side with solder balls) by wires stitched through the slot. This is then covered in a strip of mould compound visible in the image. Super fast signals, super cheap construction.